1. Field of the Invention
The present invention relates to a modulation circuit for outputting a pulse signal modulated in accordance with a value of input data by a predetermined period and an image display using the same, more particularly relates to a modulation circuit of a drive signal of a light emitting diode (LED) and an image display using the same.
2. Description of the Related Art
Since the invention of the blue LED, LED color displays that use LEDs to form pictures by pixels emitting the three primary colors have been widely and generally fabricated. An LED is highly durable can be used semipermanently, so is optimal for long-term use outdoors. Therefore, LEDs have been extensively used for large-scale displays in stadiums and event sites and for information display panels or advertisements on sides of buildings and inside railway stations. In recent years, along with the increasing luminance and lower prices of blue LEDs, such LED color displays have been spreading rapidly.
FIG. 1 is a view of a drive circuit of an LED forming a pixel of an LED display.
In FIG. 1, reference numeral 100 indicates a drive circuit and 200 an LED. In addition, Spx represents a video signal supplied to an individual pixel, and Id a current flowing through the LED 200, respectively.
The drive circuit 100 outputs a current according to the video signal Spx to the LED 200, while the LED 200 emits light according to the supplied current. An LED display is comprised of exactly the same number of circuits consisting of the drive circuits 100 and LEDs shown in FIG. 1 as that of the pixels. By making the LEDS of the pixels emit light with luminances according to the video signals Spx supplied to the pixels, a person viewing the screen can recognize a picture. The video signal Spx supplied to each pixel is generally input to the drive circuit 100 as a digital value of a certain number of bits.
FIG. 2 is a view of the waveform of the current flowing through the LED 200 in FIG. 1.
In FIG. 2, the ordinate indicates the current flowing through the LED 200 by a relative value, while the abscissa indicates time by a relative value. In addition, Ipulse indicates the peak value of the waveform of the pulse-shaped current flowing through the LED, tw the time width of the pulse portion, and T the period of the waveform,
As shown in FIG. 2, the current flowing through the LED forming a pixel of an LED display has a periodic pulse-like waveform. The luminance is controlled by pulse width modulation to make the pulse width tw variable.
In principle, the current flowing through the LED is a direct current. It is possible to change the current value in accordance with the video signal Spx to adjust the luminance, but in this case, it is necessary to finely control the current value by the drive circuit. There is the problem that the circuit for this control ends up increasing the number of parts. It is easier to increase the resolution of the time than the resolution of the current value, so in general the pulse width modulation system such as shown by the current waveform of FIG. 2 is adopted.
Due to the nature of human senses, the luminance of light blinking in a manner staying lit for less than {fraction (1/60)} of a second is perceived to have a constant luminance. Therefore, even an LED is driven by a current of the waveform shown in FIG. 2, if the period T of the current is shorter than the aforesaid time, the blinking light from the LED can be made to be perceived by people as light of a constant luminance. Further, generally, the magnitude of the luminance of an LED perceived by the human senses is proportional to the current flowing through the LED averaged over time. Therefore, the luminance changes in proportion with the duty of the pulse current.
The level of a video signal input to an LED display, however, is normalized in advance to match the luminance characteristics of a cathode ray tube (CRT). If such a video signal is input as it is to an LED, which has different luminance characteristics from a CRT pixel, the following problem arises.
FIG. 3 is a view of the relation of the luminances of an LED and CRT pixel with the level of an input signal.
In FIG. 3, the ordinate represents the luminance of an LED or CRT pixel by a relative value, while the abscissa represents the level of the signal input to an LED or a CRT pixel by a relative value. The curves indicated by A and B show the luminance characteristics of a CRT pixel and an LED, respectively.
Note that for the luminance characteristic A of a CRT pixel, the level of the signal is expressed by voltage, while for the luminance characteristic B of an LED, the level of the signal is expressed by the current flowing through the LED.
As shown in FIG. 3, the luminance of an LED has a linear relationship with the signal level, while the luminance of the CRT pixel has a nonlinear relationship with the signal level. In general, the luminance of a CRT pixel is proportional to the 2.2th power of the voltage level of the video signal. If a current proportional to a video signal normalized to match such a ce due to the above luminance characteristic of the video signal is input to the drive circuit 100 as the above video signal Spx. Specifically, for example, when driving an LED of a linear luminance characteristic by a video signal produced to match with CRT pixel emitting light of a luminance proportional to the 2.2th power of the signal level, a signal proportional to the 2.2th power of the video signal is generated to drive the LED.
In order to solve this problem, in an LED display of the related art, a signal corrected to eliminate the influence due to the above luminance characteristic of the video signal is input to the drive circuit 100 as the above video signal spx. Specifically, for example, when driving an LED of a linear luminance characteristic by a video signal produced to match with CRT pixel emitting light of a luminance proportional to the 2.2th power of the signal level, a signal proportional to the 2.2th power of the video signal is generated to drive the LED.
Summarizing the disadvantage to be solved by the invention, if the bit length of the original video signal is not sufficiently large, the binary data obtained by raising this digitalized image data to the 2.2th power is incapable of expressing fine changes of value in the region where the value of the original video signal is small. In other words, if the bit length of the digitalized video signal is small, the grey scale ends up rough in the low luminance region resulting in an unnatural picture. In order to avoid such a disadvantage, it is necessary to increase the bit length of the video signal. Specifically, in an LED display of the related art, it is necessary to generate a video signal of a length of 12 to 16 bits to reproduce a picture which had been expressed by a video signal of a length of 8 bits in the case of a CRT. If the bit length of the video signal is increased in this way, the bit length of the pulse width modulation circuits for driving the LEDs also has to be increased, so the overall circuit scale becomes larger and the cost and power consumption rise.
Further, the pulse-like waveform shown in FIG. 2 is generally generated by counting a clock signal serving as a time reference. Increasing the bit length of a video signal means increasing the number of times to count the clock signal by that extent, so when using a clock signal of the same frequency, the period T of pulse width modulation ends up longer. For example, when generating and modulating the pulse width of a 12-bit video signal, 4 bits larger than an 8-bit video signal, and comparing them with the same frequency of the clock signal, the period T of pulse width modulation becomes 16 times that of an 8-bit video signal. Since the period T of pulse width modulation is set using the characteristic of the human senses described above, if this period is too long, xe2x80x9cflickeringxe2x80x9d where the blinking of the light will be perceived by the human eye will be caused and the picture will become hard to view. Furthermore, this flickering by nature is more noticeable to the human eye in an LED display compared with a CRT, so the period T of pulse width modulation has to be several times higher than that of the usual refresh rate, for example, for example {fraction (1/50)} of a second.
To increase the bit length of a video signal and shorten the period T of pulse width modulation, it is enough to increase the frequency of the clock signal used in the pulse width modulation circuit, but this has the disadvantage of increasing the power consumption of the circuit. Further, as it is difficult to further increase the current frequency of 10 to 20 MHZ 10 or more fold, there is a limit to increasing the frequency of the clock signal.
An object of the present invention is to provide a modulation circuit outputting a pulse signal having a pulse length modulated in accordance with the value of the input data which is capable of setting the relationship between the input data and the pulse length to match with a predetermined characteristic without increasing the bit length of the input data or applying processing such as correction of the input data and an image display provided with such a modulation circuit.
To attain the above object, according to a first aspect of the present invention, there is provided a modulation circuit for outputting a pulse signal modulated in accordance with the value of input data by a predetermined period, comprising a clock generation circuit for generating and outputting a first clock pulse changing in frequency by the predetermined period; a clock counting circuit for receiving the first clock pulse, counting the first clock pulse from a predetermined initial value in an initial stage of the predetermined period, and outputting a clock count; and a pulse signal output circuit for comparing magnitudes of the clock count and the value of the input data and inverting a level of the pulse signal in the vicinity of a time when the magnitudes of the clock count and the value of the input data invert.
According to the modulation circuit of the present invention, the first clock pulse generated in the clock generation circuit is made variable in frequency in the predetermined period. The first clock pulse is counted from a predetermined initial value in the initial stage of the predetermined period in the clock counting circuit, and the count result is output as the clock count. The magnitudes of the clock count and the input data are compared in the pulse signal output circuit, and the pulse signal output by the pulse signal output circuit is inverted in level in the vicinity of the time when the magnitudes of the clock count and the value of the input data invert.
Preferably, the clock pulse generation circuit includes a frequency division setting circuit for outputting a frequency division setting changing in value by the predetermined period and a prescaler for receiving a second clock pulse and the frequency division setting, dividing the second clock pulse by a frequency division number in accordance with the frequency division setting, and outputting the first clock pulse.
According to the modulation circuit of the present invention having the above configuration, a frequency division setting changing in value by the predetermined period is generated and output at the frequency division setting circuit. The second clock pulse is divided by a frequency division number in accordance with the frequency division setting in the prescaler, and the divided signal is output as the first clock pulse. Accordingly, the period of the first clock pulse is changed by the predetermined period in accordance with the value of the frequency division setting.
Preferably, the clock pulse generation circuit includes a frequency division setting circuit for outputting a frequency division setting changing in value by the predetermined period; a prescaler for receiving the first clock pulse and the frequency division setting, dividing the first clock pulse by a frequency division number in accordance with the frequency division setting, and outputting a feedback signal; a phase comparison circuit for detecting a phase difference between a second clock pulse and the feedback signal and outputting a phase difference signal in accordance with the related phase difference; and an oscillation circuit for outputting the first clock pulse having a period in accordance with a level of the phase difference signal.
According to the modulation circuit of the present invention having the above configuration, the phase difference between the second clock pulse and the feedback signal is detected at the phase comparison circuit and a phase difference signal of a level in accordance with the related phase difference is generated and output. Then, this phase difference signal is input to the oscillation circuit, and the first clock pulse having a period in accordance with the level of the phase difference signal is generated and output at the oscillation circuit. Further, the first clock pulse is input to the prescaler, divided, and input as the period signal to the phase comparison circuit. The frequency division number of the prescaler is made variable by the frequency division setting generated by the frequency division setting circuit. The frequency division setting is generated as a signal changing by the predetermined period by the frequency division setting circuit. Accordingly, the period of the first clock pulse is made variable by the predetermined period in accordance with the value of the frequency division setting.
Preferably, the clock pulse generation circuit includes a frequency division circuit for dividing the first clock pulse by a predetermined frequency division number and outputting a frequency divided signal; a phase comparison circuit for detecting the phase difference between pulse period signal having the predetermined period and the frequency divided signal, and outputting a phase difference signal of a level in accordance with the phase difference; a variable clock period circuit for outputting a variable clock period signal varying in level by the predetermined period; and an oscillation circuit for outputting the first clock pulse having a period in accordance with the sum of levels of the variable clock period signal and the phase difference signal.
According to the modulation circuit of the present invention having the above configuration, in the frequency division circuit, the first clock pulse is divided by the predetermined frequency division number and a divided signal is output. The phase difference between the divided signal and a pulse period signal having the predetermined period is detected at the phase comparison circuit, and a phase difference signal of a level in accordance with the related phase difference is generated and output. On the other hand, the variable clock period signal varying in level by the predetermined period is generated in the variable clock period circuit. The clock period signal and the phase difference signal are input to the oscillation circuit. In the oscillation circuit, the first clock pulse having a period in accordance with the sum of levels of the clock period signal and the phase difference signal is generated and output. Accordingly, the period of the first clock pulse is changed by the predetermined period in accordance with the level of the clock period signal.
According to a second aspect of the present invention, there is provided a modulation circuit for outputting a pulse signal modulated in accordance with a value of input data by a predetermined period comprising a clock generation circuit for generating and outputting a first clock pulse having a frequency in accordance with the value of the input data; a clock counting circuit for receiving the first clock pulse, counting the first clock pulse from a predetermined initial value in an initial stage of the predetermined period, and outputting a clock count; and a pulse signal output circuit for comparing magnitudes of the clock count and the value of the input data and inverting a level of the pulse signal in the vicinity of a time when the magnitudes of the clock count and the value of the input data invert.
According to the modulation circuit of the present invention having the above configuration, the first clock pulse generated in the clock generation circuit is set in accordance with the value of the input data. The first clock pulse is counted from a predetermined initial value in the initial stage of the predetermined period in the clock counting circuit, and the count result is output as the clock count. The magnitudes of the clock count and the input data are compared in the pulse signal output circuit, and the pulse signal output by the pulse signal output circuit is inverted in level in the vicinity of the time when the magnitudes of the clock count and the value of the input data invert.
According to a third aspect of the present invention, there is provided an image display having a light emission element receiving a pulse signal modulated in accordance with a value of input data and emitting light with a luminance in accordance with the level of the pulse signal comprising a clock generation circuit for generating and outputting a first clock pulse changing in frequency by a predetermined period; a clock counting circuit for receiving the first clock pulse, counting the first clock pulse from a predetermined initial value in an initial stage of the predetermined period, and outputting a clock count; and a pulse signal output circuit for comparing magnitudes of the clock count and the value of the input data and inverting a level of the pulse signal in the vicinity of a time when the magnitudes of the clock count and the value of the input data invert.
According to the image display of the present invention having the above configuration, the first clock pulse generated in the clock generation circuit is changed in frequency by a predetermined period. The first clock pulse is counted from a predetermined initial value in the initial stage of the predetermined period in the clock counting circuit, and the count result is output as the clock count. The magnitudes of the clock count and the input data are compared in the pulse signal output circuit, and the pulse signal output by the pulse signal output circuit is inverted in level in the vicinity of the time when the magnitudes of the clock count and the value of the input data invert. The light emission element receiving the pulse signal emits light with a luminance in accordance with the level of the pulse signal.
Preferably, the clock pulse generation circuit includes a frequency division setting circuit for outputting a frequency division setting changing in value by the predetermined period and a prescaler for receiving a second clock pulse and the frequency division setting, dividing the second clock pulse by a frequency division number in accordance with the frequency division setting, and outputting the first clock pulse.
According to the image display of the present invention having the above configuration, a frequency division setting changing in value by a predetermined period is generated and output at the frequency division setting circuit. The second clock pulse is divided by a frequency division number in accordance with the frequency division setting in the prescaler, and the divided signal is output as the first clock pulse. Accordingly, the period of the first clock pulse is changed in accordance with the value of the frequency division setting by the predetermined period.
Preferably, the clock pulse generation circuit includes a frequency division setting circuit outputting the frequency division setting having the value varying by the predetermined period, a prescaler receiving the first clock pulse and the frequency division setting and outputting a feedback signal obtained by dividing the frequency of the first clock pulse by the frequency division number in accordance with the frequency division setting, a phase comparison circuit detecting a phase difference between a second clock pulse and the feedback signal and outputting a phase difference signal of a level in accordance with the related phase difference, and an oscillation circuit outputting the first clock pulses having the period in accordance with the level of the phase difference signal.
According to the image display of the present invention having the above configuration, the phase difference between the second clock pulse and the feedback signal is detected at the phase comparison circuit, and a phase difference signal of a level in accordance with the phase difference is generated and output. Then, the phase difference signal is input to the oscillation circuit, and a first clock pulse having a period in accordance with the level of the phase difference signal is generated and output in the oscillation circuit. Further, the first clock pulse is input to the prescaler and divided and input as the period signal to the phase comparison circuit. The frequency division number of the prescaler is changed by the frequency division setting generated by the frequency division setting circuit. The frequency division setting is generated by the frequency division setting circuit as a signal changing by a predetermined period. Accordingly, the period of the first clock pulse is made variable in accordance with the value of the frequency division setting by the predetermined period.
Preferably, the clock pulse generation circuit includes a frequency division circuit for dividing the first clock pulse by the predetermined frequency division number and outputting a frequency divided signal and a phase comparison circuit for detecting a phase difference between a pulse period signal having the predetermined period and the frequency divided signal and outputting a phase difference signal of a level in accordance with the related phase difference and the oscillation circuit outputs the first clock pulse having a period in accordance with a sum of levels of the variable clock period signal and the phase difference signal.
According to the image display of the present invention having the above configuration, the first clock pulse is divided by a predetermined frequency division number and the divided signal is generated and output at the frequency division circuit. The phase difference between the divided signal and a pulse period signal having the predetermined period is detected at the phase comparison circuit, and a phase difference signal of a level in accordance with the phase difference is generated and output. On the other hand, a variable clock period signal changing in level by the predetermined period is generated in the variable clock period circuit, and the clock period signal and the phase difference signal are input to the oscillation circuit. In the oscillation circuit, a first clock pulse having a period in accordance with the sum of levels of the clock period signal and the phase difference signal is generated and output. Accordingly, the period of the first clock pulse is made variable in accordance with the level of the clock period signal by the predetermined period.
According to a fourth aspect of the present invention, there is provided an image display having a light emission element receiving a pulse signal modulated in accordance with a value of input data and emitting light with a luminance in accordance with the level of the pulse signal; a clock generation circuit for generating and outputting a first clock pulse having a frequency in accordance with the value of the input data; a clock counting circuit for receiving the first clock pulse, counting the first clock pulse from a predetermined initial value in an initial stage of the predetermined period, and outputting a clock count; and a pulse signal output circuit for comparing magnitudes of the clock count and the value of the input data and inverting a level of the pulse signal in the vicinity of a time when the magnitudes of the clock count and the value of the input data invert.
According to the image display of the present invention having the above configuration, the first clock pulse generated in the clock generation circuit is set in accordance with the value of the input data. The first clock pulse is counted from the predetermined initial value in the initial stage of the predetermined period in the clock counting circuit, and the related count result is output as the clock count. The magnitudes of the clock count and the value of the input data are compared at the pulse signal output circuit, and the level of the output signal of the pulse signal output by the pulse signal output circuit is inverted in the vicinity of the time when the magnitudes of the clock count and the value of the input data invert. The light emission element receiving the pulse signal input thereto emits light with luminance in accordance with the level of the pulse signal.